Architect gives traders customizable infrastructure that reimagines access to international markets for digital assets. Backed by Cyber Fund.
About the role
As a Member of Technical Staff - Formal Verification Engineer at Architect Labs, you'll own formal verification of the AI-generated chip design artifacts, from early specifications through tape-out. You'll turn design intent into assertions, build formal environments, and work directly with designers to formally verify complex designs.
What they're looking for
- Degree: BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- RTL and Assertions: Strong SystemVerilog and SVA skills. You can read complex RTL, understand the microarchitecture, and write properties that accurately capture its intended behavior
- Formal Tools: Hands-on experience with tools such as Cadence Jasper, Synopsys VC Formal, or Siemens Questa Formal. You can build verification environments, debug failed proofs, and improve proof convergence
- Proof Techniques: Practical understanding of model checking, induction, abstraction, and assume-guarantee reasoning. You know how constraints and modeling choices affect what a proof actually establishes
- Hardware Understanding: Comfortable reasoning about control logic, pipelines, arbitration, buffering, and interface protocols, including reset behavior, backpressure, and concurrent transactions
- Engineering Rigor: Strong scripting skills in Python, Tcl, or similar languages. You build repeatable workflows and keep verification results traceable to requirements and design revisions
More about this role
Architect is a frontier AI lab for specialized computing systems. We partner with AI labs, clouds / neoclouds, quant firms, physical AI companies, fabless companies, IP providers, system companies and advanced fabs to tape-out custom hardware co-designed for their next-generation AI workloads. Our goal is to compress end-to-end software to silicon timelines, and maximize intelligence per watt and per dollar for the world. We are a small exceptional team across silicon, systems, software and frontier AI. Our team has led research teams at nearly every frontier AI lab and led chip programs for some of the most complex SoCs in the world.
As a Member of Technical Staff - Formal Verification Engineer at Architect Labs, you'll own formal verification of the AI-generated chip design artifacts, from early specifications through tape-out. You'll turn design intent into assertions, build formal environments, and work directly with designers to formally verify complex designs.
Develop and execute formal verification plans using AI for hardware blocks and subsystems. Identify critical properties, define the scope of verification, and establish clear criteria for closure.
Work with the AI...
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