Architect gives traders customizable infrastructure that reimagines access to international markets for digital assets. Backed by Cyber Fund.
About the role
As our first Physical Design engineer, you'll build the PD function from scratch and extend our AI system from spec-to-netlist to tapeout-ready GDS. You'll own the methodology and hands-on execution for physical implementation at 3nm, 2nm, and future leading-edge nodes. Build the methodology: Establish and qualify the complete netlist-to-GDS flow, including PDKs, libraries, tools, constraints, automation, and reproducible regression infrastructure.
What they're looking for
- Tapeout ownership: Multiple production tapeouts, with direct physical implementation and signoff responsibility at 3nm or 2nm and experience leading full-chip closure
- Methodology development: A track record of building production PD methodology from scratch for advanced nodes, including PDK/library qualification, tool evaluation, and deployment across chip programs
- Technical depth: Deep expertise in hierarchical implementation, multi-mode multi-corner timing analysis, variation, clocking, congestion, low-power design, extraction, and power integrity
- EDA expertise: Recent hands-on mastery of Synopsys Fusion Compiler/ICC2 or Cadence Innovus, along with commercial timing, extraction, power integrity, and physical verification tools
- Automation: Strong Tcl and Python skills, with experience building maintainable flow scripts, automated checks, regressions, and actionable PPA reporting
- Technical leadership: Ability to independently establish the flow, debug difficult closure problems, and explain implementation trade-offs to hardware, software, and AI teams
More about this role
Architect is a frontier AI lab for custom silicon. We partner with frontier labs, clouds / neoclouds, physical AI companies, OEMs and advanced fabs to tape-out custom chips co-designed for next-generation AI workloads. Our goal is to compress end-to-end software to silicon timelines, and maximize intelligence per watt and per dollar for the world. We are a small exceptional team across silicon, systems, software and frontier AI. Our team have led research teams at nearly every frontier AI lab, and at some of the most complex SoCs in the world.
As our first Physical Design engineer, you'll build the PD function from scratch and extend our AI system from spec-to-netlist to tapeout-ready GDS. You'll own the methodology and hands-on execution for physical implementation at 3nm, 2nm, and future leading-edge nodes.
Build the methodology: Establish and qualify the complete netlist-to-GDS flow, including PDKs, libraries, tools, constraints, automation, and reproducible regression infrastructure.
Own implementation: Personally drive block and full-chip floorplanning, power planning, placement, clock tree synthesis, routing, and ECOs to meet demanding PPA targets.
Drive signoff: Define...
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