Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. What sets us apart is our relentless pursuit of innovation. Backed by Redpoint.
About the role
Our Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet products used in enterprise campuses, hyperscaler data centers, and bleeding-edge AI clusters. The team is responsible for the end-to-end design and development of advanced hardware solutions that meet the demands of modern networking environments. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- 5 years or more of hands-on experience in Verilog/SystemVerilog RTL design
- Proven background in Control Path design
- Direct experience with On-Chip Bus interfaces (e.g., I2C, SPI, MDIO, PCIe, AXI)
- Local to the area
More about this role
You will work closely with cross-functional hardware, software, and manufacturing engineering teams to innovate new system architectures and drive FPGA development from initial concept to final delivery.
Our Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet products used in enterprise campuses, hyperscaler data centers, and bleeding-edge AI clusters. The team is responsible for the end-to-end design and development of advanced hardware solutions that meet the demands of modern networking environments.
As a core member of the FPGA Design and Verification team, you will drive the development of high-performance control path FPGAs powering Arista’s flagship data center platforms. You will own the full design lifecycle—from gathering architectural requirements and reviewing board schematics to executing rigorous verification, leading system bring-up, and supporting production deployment.
- RTL Development & Verification: Develop, integrate, simulate, and verify Verilog and SystemVerilog RTL code, including custom testbench creation.
- FPGA Flow Implementation: Execute the full FPGA development flow, including synthesis, place and...
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