Broadcom delivers semiconductors and infrastructure software for global enterprises’ most complex, mission-critical needs.
About the role
Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
What they're looking for
- Bachelors and 8+ years of related experience, or Masters degree and 6+ years of related experience
- Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and oth ers)
- Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)
- Logic BIST design and debug experience
- Well-versed in ATPG vector generation, simulation, and debugging. (TetraMax, Fastscan)
- Experience in Verilog coding, testbench generation & simulation
More about this role
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Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production.
The candidate would be required to work on various phases of SoC DFT related activities for APD's designs – DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.
Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC
Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
Responsibilities includes...
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