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DFT Engineer

Broadcom · USA-CA San Jose Innovation Drive · On-site

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About Broadcom

Broadcom delivers semiconductors and infrastructure software for global enterprises’ most complex, mission-critical needs.

About the role

DFT Pattern post-silicon support: ATPG and MBIST DFT patterns generation, bringup and debug Yield Enhancement: Monitor wafer sort (CP) and final test (FT) yield, binning distribution, and parametric data. Drive continuous improvement plans to achieve aggressive yield and cost targets.

What they're looking for

  • Deep understanding of CMOS device physics, semiconductor manufacturing processes (Lithography, Etch, Deposition, CMP, Implant), and electrical testing methodologies
  • Knowledge of Testability techniques and features (SCAN, MBIST, bscan.) covering digital logic domain, embedded memories and PHY/IO’s
  • Scan flow development, ATPG pattern generation, verification and coverage analysis
  • Experience working with Mentor/Siemens DFT Tessent tool for scan/MBIST/bscan/IJTAG pattern generation and debug
  • Post Silicon experience in Pattern conversion for Testers, Pattern Bring-up & Debug, Silicon Characterization etc
  • Strong Pre/Post Silicon debugging, analytical and independent problem solving ability
More about this role

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Broadcom’s Core Switching Group division is seeking a candidate for a DFT engineer. Products include networking switches for Scale up and Scale Out for traditional and AI data centers. This position is at our R&D center in San Jose, CA. The successful candidate will have hands-on experience for DFT ATPG and mbist pattern debug and drive defect reduction, optimize wafer sort & final test, and maximize yield across our product portfolio.

DFT Pattern post-silicon support: ATPG and MBIST DFT patterns generation, bringup and debug

Yield Enhancement: Monitor wafer sort (CP) and final test (FT) yield, binning distribution, and parametric data. Drive continuous improvement plans to achieve aggressive yield and cost targets.

Root Cause Analysis: Perform scan diagnostic, mbist and repair debug, resolve yield excursions. Correlate electrical failures to inline fab metrology, defect density, and process tool data.

Failure Analysis (FA): Support ATPG scan diag and guide physical...

Read the full posting on Broadcom's site ↗

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