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Digital Design Verification Engineer

Broadcom · 2 Locations · On-site

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About Broadcom

Broadcom delivers semiconductors and infrastructure software for global enterprises’ most complex, mission-critical needs.

About the role

Operate with a high degree of autonomy, taking designs from initial specification through to timing closure and physical design hand-off Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure project milestones are met on schedule

What they're looking for

  • BSEE required, MSEE/PHD preferred
  • 5+ years of industry experience with a focus on SoC integration, UVM test bench setup and design debug
More about this role

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The ideal candidate has a proven track record of working on setting up testbenches for Design Verification using UVM on large designs.

Operate with a high degree of autonomy, taking designs from initial specification through to timing closure and physical design hand-off

Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure project milestones are met on schedule

High proficiency in UVM

BSEE required, MSEE/PHD preferred

5+ years of industry experience with a focus on SoC integration, UVM test bench setup and design debug.

The annual base salary range for this position is USD 101,000.00 To USD 162,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award...

Read the full posting on Broadcom's site ↗

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