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About the role
Join the team behind Xcelium , the industry-leading logic simulator, to architect the next generation of hardware verification technology. As a Senior Engineer in the System Verification Group, you will be at the forefront of EDA innovation, evolving the Xcelium simulator to meet the staggering complexity of future AI and hyperscale chip designs. You will be part of an innovative, geographically distributed team dedicated to advancing the capabilities of RTL/logic simulation for semiconductor technology.
What they're looking for
- MS in Computer Science or Electrical Engineering with a minimum of 12 years of experience OR PhD with a minimum of 10 years of experience
- 10+ years of experience in EDA software development
- Strong background in RTL/Logic Simulation, SDC constraints and Timing Analysis especially path exceptions handling in a STA tool
- Excellent programming skills in C/C++ and a deep understanding of SystemVerilog or Verilog
- Experience in multi-threaded/ concurrent programming
- Ability to quickly learn new technologies and adapt to project requirements
More about this role
Join the team behind Xcelium , the industry-leading logic simulator, to architect the next generation of hardware verification technology. As a Senior Engineer in the System Verification Group, you will be at the forefront of EDA innovation, evolving the Xcelium simulator to meet the staggering complexity of future AI and hyperscale chip designs. You will be part of an innovative, geographically distributed team dedicated to advancing the capabilities of RTL/logic simulation for semiconductor technology. The work environment encourages collaboration, technical excellence, and continuous learning.
We are looking for experienced C++ software engineers who thrive on "impossible" scaling challenges and want to invent the algorithms that will power tomorrow’s silicon.
- Enhance and support Xcelium RTL/logic simulator engine to add new features and extend existing features.
- Enhance and support Timing Constraints Verification technology used inside Xcelium simulator.
- The role involves designing, tuning, and innovating graph algorithms involving SDC constraints support on multi‑billion‑node graphs.
- Conduct deep-dive bottleneck analysis and implement performance optimizations in...
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