Startups · AI

Sr. Staff Power Performance Architect

d-Matrix · Santa Clara · Remote

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About d-Matrix

d-Matrix is redefining AI inference with memory-centric compute built for ultra-low latency, greater efficiency, and scalable AI infrastructure.

About the role

d-Matrix is looking for a Senior Staff Power Performance Architect to own pre-silicon power estimation across our next-generation AI accelerators. In this role, you will drive both RTL-level and physical-design-level power estimation, and build an architectural power estimation tool that models power from system configuration and die-level metrics for AI workloads.

What they're looking for

  • Exposure to power estimation and performance metrics such as TDP, PMAX, EDP, Peak, and Average
  • Familiarity with power/frequency scaling techniques (DFS, DVFS, AFS, AVFS)
  • Familiarity with power delivery network (PDN) analysis, including resonance, impedance (Z(f)), and voltage droop analysis
More about this role

At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.

We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI.

d-Matrix is looking for a Senior Staff Power Performance Architect to own pre-silicon power estimation across our next-generation AI accelerators. In this role, you will drive both RTL-level and physical-design-level power estimation, and build an architectural power estimation tool that models power from system configuration and die-level metrics for AI workloads. You will partner closely with front-end architects, DV engineers, and backend design teams to identify power activity windows, define performance monitoring requirements, and translate that analysis into hardware capability...

Read the full posting on d-Matrix's site ↗

Hardware Engineering

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