d-Matrix is redefining AI inference with memory-centric compute built for ultra-low latency, greater efficiency, and scalable AI infrastructure.
About the role
This is a hands-on, transistor-level analog design role owning the clocking subsystem of d-Matrix's high-speed SerDes on our IO chiplet — including the PLL, DLL, phase interpolator, high-frequency clock distribution, and clock and data recovery (CDR) loop. This block set most often determines whether a link closes, and you will personally carry your designs from specification through silicon characterization.
More about this role
At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.
We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI.
This is a hands-on, transistor-level analog design role owning the clocking subsystem of d-Matrix's high-speed SerDes on our IO chiplet — including the PLL, DLL, phase interpolator, high-frequency clock distribution, and clock and data recovery (CDR) loop. This block set most often determines whether a link closes, and you will personally carry your designs from specification through silicon characterization. The work spans porting proven clocking blocks to new process nodes and ground-up design for our next-generation link, partnering closely with datapath, DSP, digital, and firmware teams...
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