Density shows you how people use your space and helps you get more out of every square foot. Backed by Kleiner Perkins and South Park Commons.
About the role
Own the physical layout of the advanced packages our AI accelerator silicon ships in. You'll take multi-die 2.5D and 3D packages from bump map through tapeout release — defining substrate and interposer stackups, planning bump and ball maps against the die floorplan, routing high-density escape and HBM-class channels, and building the power delivery that feeds hundreds of amps into the accelerator.
What they're looking for
- 8+ years of package layout experience on high-performance designs, including 2.5D / 3D and multi-die packages (CoWoS, EMIB, InFO, fan-out, or equivalent interposer technologies)
- Hands-on with industry-standard package layout tools (Cadence Allegro Package Designer / SiP Layout, Siemens Xpedition Package Designer, or equivalent) and package DRC/LVS flows
- Demonstrated ability to work closely with architecture, physical design, SI/PI, thermo-mechanical, and OSAT partners to converge and sign off complex package designs
More about this role
Own the physical layout of the advanced packages our AI accelerator silicon ships in. You'll take multi-die 2.5D and 3D packages from bump map through tapeout release — defining substrate and interposer stackups, planning bump and ball maps against the die floorplan, routing high-density escape and HBM-class channels, and building the power delivery that feeds hundreds of amps into the accelerator. You'll sit between the die and the board, co-designing with physical design on one side and PCB layout on the other, and you'll own the design release our substrate suppliers and OSATs build from. When the package is the thing standing between silicon and a working system, this is the role that closes it.
- Own package substrate and interposer layout end to end; stackup definition, bump and ball map planning, RDL and escape routing, and design release to substrate suppliers and OSATs
- Own die-to-package-to-board co-design, partnering with physical design on bump placement and floorplan and with PCB layout on the package-board interface
- Close package DRC/LVS and netlist verification against OSAT and substrate vendor design rules, and drive rule negotiation where the design requires...
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