Startups · AI

Performance Verification Engineer

Density · Mountain View, CA · On-site

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About Density

Density shows you how people use your space and helps you get more out of every square foot. Backed by Kleiner Perkins and South Park Commons.

About the role

We are looking for engineer with strong performance testing background. You will be responsible for end to end performance correlation for our AI accelerator silicon, including architecting the test bench as well as defining the testing strategies. This engineer will be working closely with software team and silicon design teams to drive DensityAI's AI accelerator program from first silicon through scale-out.

What they're looking for

  • Exceptional abilities in performance modeling and verification and tool-flow ownership
  • Master's + 8 years of experience performance validation/verification on complex SOCs
  • Demonstrated ability to debug, co-relate and drive convergence on performance model to RTL alongside RTL designers and architects
  • Hands-on with industry-standard tools for tracing, compilation and related workflows
  • (Optional) Processor verification, compiler exposure, hardware validation
More about this role

We are looking for engineer with strong performance testing background. You will be responsible for end to end performance correlation for our AI accelerator silicon, including architecting the test bench as well as defining the testing strategies.

This engineer will be working closely with software team and silicon design teams to drive DensityAI's AI accelerator program from first silicon through scale-out.

  • Own block-level and SOC-level Performance verification and correlation, debug for our AI accelerator silicon
  • Work closely with software and hardware architects to create tests for performance verification and participate in future architectural decisions
  • Exceptional abilities in performance modeling and verification and tool-flow ownership
  • Master's + 8 years of experience performance validation/verification on complex SOCs
  • Demonstrated ability to debug, co-relate and drive convergence on performance model to RTL alongside RTL designers and architects
  • Hands-on with industry-standard tools for tracing, compilation and related workflows
  • (Optional) Processor verification, compiler exposure, hardware validation

Final offers depend on level, location, and skills...

Read the full posting on Density's site ↗

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