Startups · AI

RTL Engineer

Density · Mountain View, CA · On-site

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About Density

Density shows you how people use your space and helps you get more out of every square foot. Backed by Kleiner Perkins and South Park Commons.

About the role

Design the RTL that defines our AI accelerator. You'll architect and implement the digital blocks — compute datapath, memory subsystem, on-chip interconnect, and control logic — from microarchitecture spec through synthesis-ready, timing-clean RTL, and own those blocks end-to-end with architecture, DV, physical design, and DFT all the way to silicon.

What they're looking for

  • Strong digital-design fundamentals and expert Verilog/SystemVerilog RTL
  • 5+ years designing complex digital blocks/SoCs taken to silicon
  • Solid microarchitecture skills — pipelining, datapath/control, FIFOs, arbitration, memory subsystems, on-chip interconnect/NoC
  • Synthesis & timing awareness — writing synthesizable RTL, SDC constraints, STA, clock/power gating, CDC, lint
  • Demonstrated collaboration with DV, PD, and DFT across the full RTL2GDS flow to tapeout
  • Scripting (Python/Tcl/) for design automation
More about this role

Design the RTL that defines our AI accelerator. You'll architect and implement the digital blocks — compute datapath, memory subsystem, on-chip interconnect, and control logic — from microarchitecture spec through synthesis-ready, timing-clean RTL, and own those blocks end-to-end with architecture, DV, physical design, and DFT all the way to silicon.

  • Own RTL design of digital blocks/subsystems for our accelerator — microarchitecture definition, SystemVerilog implementation, and integration
  • Translate architectural specs into efficient, synthesizable RTL that meets power/performance/area (PPA) targets
  • Drive microarchitecture trade-offs — pipelining, datapath vs. control, clock/power gating — for high-performance, low-power design
  • Partner with DV on verification, PD on synthesis/timing/floorplan closure, and DFT on testability
  • Own block-level quality: synthesis, timing/constraints (SDC, STA), lint, and CDC signoff
  • Contribute to architecture definition and design reviews; debug across simulation, emulation, and post-silicon bring-up
  • Use and develop AI-assisted tool flows to accelerate design and verification
  • Strong digital-design fundamentals and expert...

Read the full posting on Density's site ↗

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