Efficient Computer builds the world's most energy-efficient general-purpose AI chips, delivering up to 100× better efficiency than low-power CPUs. Backed by USV.
About the role
We're looking for a Lead Physical Design Engineer to take end-to-end ownership of SOC -top for our next-generation SoCs. This is a hands-on, high-accountability role — you'll be the single point of ownership driving the full chip from block integration through timing, power, signal integrity, and physical closure to tapeout-ready GDS. You'll work closely with block-level PD owners, DFT, package/IO teams, and the architecture team.
What they're looking for
- Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
- 8-12+ years of physical design experience, with at least 2-3 full tapeouts at the chip-top/SoC integration level (not just block-level)
- Deep hands-on experience with advanced nodes
- Proven track record owning full-chip timing closure across multiple corners/modes on a complex SoC
- Strong PDN/IR-drop/EM analysis experience (Voltus or equivalent)
- Experience with chip-level DFT integration (scan stitching, MBIST, JTAG)
More about this role
Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution
We're looking for a Lead Physical Design Engineer to take end-to-end ownership of SOC -top for our next-generation SoCs. This is a hands-on, high-accountability role — you'll be the single point of ownership driving the full chip from block integration through timing, power, signal integrity, and physical closure to tapeout-ready GDS. You'll work closely with block-level PD owners, DFT, package/IO teams, and the architecture team. This role will be in the newly formed hardware engineering group and will focus on designing in state of the art finfet technologies.
This is a unique...
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