Co-designed chips, racks, and software to push the pareto frontier to best-in-class throughput and interactivity. Backed by Kleiner Perkins and Sequoia.
About the role
Own HAPS bring-up. Take RTL from the design teams and get it running on the prototype — partitioning, multi-FPGA timing closure, clocking, memory mapping, and full-chip assembly. Expand platform coverage. Stand up new subsystem configurations so more of the chip is available to software earlier. Each new partition you enable unblocks a team.
What they're looking for
- Hands-on FPGA prototyping experience — HAPS, Protium, proFPGA, S2C, or similar — covering partitioning, synthesis, timing closure, bring-up, and debug
- Strong SystemVerilog and Verilog, with a working understanding of what synthesizes well for FPGA and what doesn't
- Solid C/C++ and Linux system development
- Scripting fluency for automation — Python, TCL, shell
- Comfort debugging failures you didn't cause, in code you didn't write, for users who need an answer today
More about this role
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference . Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Own HAPS bring-up. Take RTL from the design teams and get it running on the prototype — partitioning, multi-FPGA timing closure, clocking, memory mapping, and full-chip assembly.
Expand platform coverage. Stand up new subsystem configurations so more of the chip is available to software earlier. Each new partition you enable unblocks a team.
Support your users. Firmware, driver, and software engineers are your customers. You'll help them get running, triage their failures, and figure out whether the bug is theirs, the RTL's, or the platform's.
Debug hard problems. Trace issues across FPGA boundaries with waveform capture, protocol analyzers, and whatever tooling you have to build yourself.
Bring up interfaces. PCIe, Ethernet, HBM and memory models, JTAG,...
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