Co-designed chips, racks, and software to push the pareto frontier to best-in-class throughput and interactivity. Backed by Kleiner Perkins and Sequoia.
About the role
We are seeking a Formal Verification Engineer to join our ASIC Design Verification team. You will drive formal verification across the custom IP, interface IP, and SoC subsystems that power our ASICs, including compute arrays, DMA engines, NoCs, memory systems, PCIe, Ethernet, CPU subsystems, low-power peripherals, and vendor IP wrappers.
What they're looking for
- 5+ years of design verification experience, including significant hands-on formal verification experience on complex digital designs or shipping silicon
- Strong proficiency with SystemVerilog, SystemVerilog Assertions, and formal verification methodology
- Experience with commercial formal tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal
- Strong understanding of digital design, computer architecture, datapaths, interconnects, memory systems, and standard SoC interfaces
- Ability to model complex design behavior using assumptions, abstractions, constraints, cut-points, checkers, and reference models
- Strong debugging skills across RTL, specifications, formal counterexamples, simulation waveforms, and verification reports
More about this role
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference . Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
We are seeking a Formal Verification Engineer to join our ASIC Design Verification team. You will drive formal verification across the custom IP, interface IP, and SoC subsystems that power our ASICs, including compute arrays, DMA engines, NoCs, memory systems, PCIe, Ethernet, CPU subsystems, low-power peripherals, and vendor IP wrappers. You will work closely with architects, RTL designers, DV engineers, emulation teams, and software/firmware teams to prove design correctness, expose deep corner-case bugs, and improve verification closure across the full chip.
Define and drive formal verification strategy across the ASIC DV team for complex IP blocks, interface subsystems, and SoC integration logic.
Develop formal verification plans covering functional...
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