Co-designed chips, racks, and software to push the pareto frontier to best-in-class throughput and interactivity. Backed by Kleiner Perkins and Sequoia.
About the role
Etched is building a new category of AI hardware: frontier inference clusters. As a top-level PD engineer, you will own full-chip implementation—encompassing floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs—from synthesis through to GDSII completion. You will lead critical efforts in these areas, leveraging our PD flows to drive aggressive PPA optimization and timing closure.
What they're looking for
- 10+ years of previous experience with chip planning, top level PD, floorplanning
- Experience with top-level and full-chip closure on advanced process nodes (5nm and below)
- Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows
- Experience with Synopsys PrimeTime and Cadence Tempus for timing signoff
- Experience with Pegasus or Calibre for physical verification signoff
- Experience with hierarchical timing budgeting, constraint management, and ECO closure
More about this role
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference . Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Etched is building a new category of AI hardware: frontier inference clusters. As a top-level PD engineer, you will own full-chip implementation—encompassing floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs—from synthesis through to GDSII completion. You will lead critical efforts in these areas, leveraging our PD flows to drive aggressive PPA optimization and timing closure. You will collaborate closely with RTL designers to provide actionable feedback, ensuring we iterate at unprecedented speeds to bring our products to market.
Own full-chip clocking across all PVT corners and modes.
Manage MMMC (Multi-Mode Multi-Corner) timing closure at the top level.
Own timing constraints and hierarchical timing budgeting between...
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