Co-designed chips, racks, and software to push the pareto frontier to best-in-class throughput and interactivity. Backed by Kleiner Perkins and Sequoia.
About the role
We are looking for a Power Integrity (PI) Engineer to join our platform electrical engineering team. In this role, you will own the power integrity methodology for high-power PCB and system designs — from early architecture through final release — ensuring robust power delivery to high-performance ASICs and supporting components across all operating conditions.
What they're looking for
- B.S. or M.S. in Electrical Engineering or a closely related discipline
- 5+ years of hands-on PI experience on high-current, high-performance designs (ASIC/CPU/GPU power delivery, server boards, or accelerator platforms)
- Proficiency with industry PI EDA tools (Ansys SIwave, Cadence Sigrity PowerDC/PowerSI/OptimizePI, or equivalent)
- Strong understanding of target impedance methodology, decoupling network design, plane resonances, and anti-resonance mitigation
- Experience with DC IR-drop analysis, current density limits, and via/plane current-carrying capacity
- Working knowledge of VRM fundamentals: buck converter operation, multiphase design, transient response, and load-line/AVP concepts
More about this role
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference . Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
We are looking for a Power Integrity (PI) Engineer to join our platform electrical engineering team. In this role, you will own the power integrity methodology for high-power PCB and system designs — from early architecture through final release — ensuring robust power delivery to high-performance ASICs and supporting components across all operating conditions.
Perform pre- and post-layout PDN analysis for high-current ASIC power rails: target impedance profiling, decoupling capacitor selection and placement optimization, and plane resonance analysis.
Execute DC IR-drop and current density simulations; define copper weight, plane shapes, via stitching, and layer allocation requirements for PCB designers.
Conduct AC impedance analysis from VRM output...
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