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Physical Design Engineer, 3D Technology

Google · United States · On-site

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About Google

Learn more about Google. Explore our innovative AI products and services, and how we. Backed by Kleiner Perkins.

About the role

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU.

What they're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
  • 4 years of experience with physical design and 3D integration technologies, such as 3D-IC, 2.5D, chip stacking, vertical stacking, Integrity, or Through-Silicon Vias (TSV)
  • Experience running industry standard tools for chip design, such as Synopsys, Cadence, Siemens EDA/Mentor Graphics
More about this role
  • Drive development of a leading edge 3D technology platform for custom, high performance ASIC’s and SoC’s, from design through manufacturing, packaging, and test.
  • Optimize digital blocks for performance, power, area, and reliability using physical design and circuit techniques.
  • Define optimal methodologies by investigating performance, power, and area across different technology nodes and implementation techniques.
  • Work with our physical design, technology, circuits, and architecture teams plus IP partners in advanced CMOS nodes.
  • Design and build custom circuits at the transistor and gate levels to support physical design and floorplan optimization.
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 4 years of experience with physical design and 3D integration technologies, such as 3D-IC, 2.5D, chip stacking, vertical stacking, Integrity, or Through-Silicon Vias (TSV).
  • Experience running industry standard tools for chip design, such as Synopsys, Cadence, Siemens EDA/Mentor Graphics.
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science,...

Read the full posting on Google's site ↗

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