About Google
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About the role
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU.
What they're looking for
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 10 years of experience in static timing analysis (STA), including 5 years of experience in a technical leadership capacity
- Experience achieving full-chip timing convergence and authoring, reviewing, or validating timing constraints (e.g., Synopsys Design Constraints (SDC))
- Experience using tool command language (Tcl) commands for timing analysis, timing closure, parasitic extraction, noise glitch, or crosstalk
- Experience using electronic design automation (EDA) tools (e.g., PrimeTime, Tempus, Timevision, or STAR-RC)
- Experience analyzing cross-chip clock distribution networks
More about this role
- Lead effort for timing constraint creation and validation, timing analysis and timing Engineering Change Order (ECO) creation, and final timing sign-off for complex ASICs.
- Drive both static timing analysis methodology development and support, as well as chip implementation and timing signoff execution.
- Develop, support and execute implementation flows around industry-standard static timing and parasitic extraction tools.
- Interface with the broader team to triage and resolve reported technical issues, escalating complex tool-related problems to Electronic Design Automation (EDA) vendors and deliver timely and effective solutions.
- Lead collaboration with RTL design and DFT team for high quality integrations and timing constraints.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience in static timing analysis (STA), including 5 years of experience in a technical leadership capacity.
- Experience achieving full-chip timing convergence and authoring, reviewing, or validating timing constraints (e.g., Synopsys Design Constraints (SDC)).
- Experience using tool...
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