About Google
Learn more about Google. Explore our innovative AI products and services, and how we. Backed by Kleiner Perkins.
About the role
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
What they're looking for
- 7 years of experience working in ASIC power analysis & optimization, including experience with production chips
- Experience in tape-outs of chips
- Experience interacting and collaborating with silicon foundries and other external vendors for the tapeout process
- Experience with Verilog and industry-standard EDA tools for power analysis & optimization design (e.g., PP-RTLA, PowerArtist, PrimeTime-PX, PrimeTime, Cadence Innovus, Synopsys Fusion Compiler)
- Experience with scripting languages (e.g., Perl, Tcl) for automation of power analysis & optimization flows
- Software development experience
More about this role
- Architect advanced technology node power solutions and establish use case budgets with block and full-chip estimations.
- Lead and drive the automation and integration of power analysis processes—including RTL power analysis, optimization, IP selection, physical design, and timing closure—into our automated flow.
- Apply hardware expertise to build, create, and integrate software components for automated early- and late-stage power analysis and optimization.
- Partner with systems power and cross-functional teams to define, execute, and advocate for power management and reduction methodologies from SoC architecture through sign-off.
Specify requirements for power management IPs while managing their design, integration, and post-silicon validation.
- 7 years of experience working in ASIC power analysis & optimization, including experience with production chips
- Experience in tape-outs of chips
- Experience interacting and collaborating with silicon foundries and other external vendors for the tapeout process
- Experience with Verilog and industry-standard EDA tools for power analysis & optimization design (e.g., PP-RTLA, PowerArtist, PrimeTime-PX, PrimeTime, Cadence Innovus,...
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