We make the best chips physically possible for the large model needs of frontier labs.
About the role
Define the architecture for MatX’s AI compute subsystem, including ISA, connectivity, memories, and control.. Collaborate closely with Research, SW, and HW teams to ensure we architect just-right silicon for workloads, programmability, and PPA.
What they're looking for
- Strong background in computer architecture, especially AI accelerators, GPUs, TPUs, vector processors, SIMD, VLIW, or other parallel compute architectures
- Experience translating workloads into hardware architecture
- Solid microarchitecture fundamentals
- First-principles understanding of latency, throughput, utilization, and scalability
- Familiarity with numeric formats, quantization, rounding, and precision/performance tradeoffs
- Programming, code optimization, or kernel-level performance analysis experience
More about this role
MatX designs hardware tailored for the world’s best AI models. Our hardware will make a given level of intelligence available 3-5 years sooner. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the world’s largest models. MatX is seeking an Architect to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The successful candidate for this role will be responsible for delivering performant silicon architecture at the full-chip or subsystem level.
MatX is seeking an AI Accelerator Compute Architect to help define the compute architecture for our next-generation GenAI accelerators.
Define the architecture for MatX’s AI compute subsystem, including ISA, connectivity, memories, and control..
Derive architectural requirements from AI use cases.
Conduct analytical and empirical performance analysis.
Collaborate closely with Research, SW, and HW teams to ensure we architect just-right silicon for workloads, programmability, and PPA.
Work through power, area, performance tradeoffs with stakeholders.
Support test plan reviews, first-silicon bring-up, and post-silicon...
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