We make the best chips physically possible for the large model needs of frontier labs.
About the role
MatX is building next-generation AI compute infrastructure for large-scale LLM training and inference. We are looking for an experienced PCB Layout Engineer to design and deliver high-speed, high-power, high-density printed circuit boards for our AI chip, compute tray, and rack-scale platform. This is a hands-on role where layout quality directly impacts signal integrity, power integrity, and system performance.
More about this role
MatX is building next-generation AI compute infrastructure for large-scale LLM training and inference. We are looking for an experienced PCB Layout Engineer to design and deliver high-speed, high-power, high-density printed circuit boards for our AI chip, compute tray, and rack-scale platform. This is a hands-on role where layout quality directly impacts signal integrity, power integrity, and system performance.
What You'll Do Here
Own PCB layout from floorplanning through final Gerber release for complex, high-layer-count boards (AI accelerator boards, compute trays, backplanes)
Design high-speed differential pair and controlled impedance routing for PCIe Gen5/6, CXL, and Ethernet 112G/224G interfaces, including length matching and timing constraints per SI/PI guidelines
Plan stack-ups (layer assignment, impedance control, via structure, laminate selection) and place/route complex BGA packages, including AI ASICs
Design power delivery networks (PDN) — VRM placement, decoupling capacitors, and power planes to meet PI requirements, partnering with SI/PI engineers on simulation and pre/post-layout analysis
Ensure DFM/DFT/DFA compliance (test points, via-in-pad, back-drill, assembly...
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