We make the best chips physically possible for the large model needs of frontier labs.
About the role
Develop and maintain power estimation methodologies for AI accelerator SoCs. Build and calibrate energy models for early architectural exploration, design trade-off analysis, and power target definition.
What they're looking for
- BS or MS in Electrical Engineering, Computer Engineering, or related field
- 8+ years of industry experience in SoC, AI accelerator, GPU, networking ASIC, or high-performance digital design
- Strong understanding of computer architecture and SoC design
- Experience with ASIC low-power design techniques
- Experience performing RTL and gate-level power analysis
- Strong analytical and debugging skills
More about this role
MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies.
Develop and maintain power estimation methodologies for AI accelerator SoCs.
Build and calibrate energy models for early architectural exploration, design trade-off analysis, and power target definition.
Perform RTL, gate-level, and post-layout power analysis across major SoC subsystems.
Analyze AI workloads and application use cases to identify opportunities for dynamic and static power reduction.
Drive power optimization across compute, memory, interconnect, PCIe, HBM, clock/reset, and other SoC subsystems.
Collaborate with architects and RTL designers to implement power-efficient...
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