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SOC Micro-Architect and RTL Designer

MatX · Mountain View (HQ) or Remote · Remote

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About MatX

We make the best chips physically possible for the large model needs of frontier labs.

About the role

Contribute to MatX’s silicon architecture-to-design methodology with a scalable solution across blocks, subsystems, fullchip design Own entire subsystem or subsets and/or chip-level silicon design deliverables from micro-architecture to sign-off ready design

What they're looking for

  • Concept-to-silicon experience in driving silicon design for subsystems and/or top-level functions with ASICs and SOCs from an architecture specification to production silicon
  • 5+ years or more experience with SystemVerilog, Python, C/C++ and similar scripting and programming languages for chip design and related flows
  • Production-proven experience on silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, memory management and related functionalities
  • Experience with testing your designs and working closely with verification teams towards performance and coverage closure goals
  • Hands-on experience with design synthesis, equivalence checking, design lint, clock-domain-crossing and related flows to take designs to high quality sign-off
  • Experience on DFT and physical design concepts and methodologies to achieve high test coverage and best-in-class timing, power and area for designs working with experts in these areas to take designs to sign-off
More about this role

MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies.

Contribute to MatX’s silicon architecture-to-design methodology with a scalable solution across blocks, subsystems, fullchip design

Own entire subsystem or subsets and/or chip-level silicon design deliverables from micro-architecture to sign-off ready design

Plan and drive intermediate and sign-off reviews on micro-architecture and design specifications, execution progress, area and timing closure towards various silicon milestones including design freeze and tapeout

Work closely with the verification, DFT, and physical design co-owners of the subsystem/block in question and deliver...

Read the full posting on MatX's site ↗

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