Neurophos develops photonic AI processing technology that focuses on hardware solutions for accelerating artificial intelligence inference by replacing traditional electronic compute elements with Optical Processing Units (OPUs). Backed by Purple Arch Ventures.
About the role
We're hiring the Design Verification Lead for the digital design team. You'll own verification for our electronic IC from module-level simulation through SoC integration, gate-level signoff, and into the validation plan. Verification here is being built from an early stage, so you'll define the UVM methodology we standardize on, set up and run the Palladium emulation environment yourself, and extend the FPGA-based harness we're already using to run real code against modules.
What they're looking for
- 8 to 15 years in design verification, including leading verification on a GPU-class or complex compute ASIC through tapeout
- Deep expertise in UVM and SystemVerilog, including ownership of testbench architecture, formal verification, coverage analysis, and CI/CD methodology
- Gate-level simulation experience. You know what gate sim costs you in visibility and where it belongs in a tapeout schedule
- Verification experience on a chip with many independently developed blocks and analog components, including integration of analog models
- Comfort standing up a verification environment end-to-end, including emulation infrastructure
- Breadth across the flow, from module-level simulation through SoC integration and into validation planning
More about this role
The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.
Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.
We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.
Join us and shape...
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