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Staff Technical Program Manager, ASIC

Neurophos · Austin, Texas · On-site

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About Neurophos

Neurophos develops photonic AI processing technology that focuses on hardware solutions for accelerating artificial intelligence inference by replacing traditional electronic compute elements with Optical Processing Units (OPUs). Backed by Purple Arch Ventures.

About the role

The Electronic IC (EIC) is the high-speed mixed-signal ASIC at the heart of our optical compute engine. It drives, reads out, and controls our photonic hardware and connects it to the rest of the system. We are looking for an experienced hardware TPM to drive the EIC program end-to-end: from architecture convergence with our chip architects, through design, verification, physical design, and tapeout at a leading-edge foundry, into post-silicon bring-up and system integration.

What they're looking for

  • BS in Electrical/Computer Engineering or equivalent (MS preferred)
  • 10+ years in ASIC/SoC development , as a TPM/EPM (or equivalent lead role) on complex silicon programs
  • 2+ complete silicon programs taken from architecture/specification through tapeout at a reputable foundry , with at least one carried through post-silicon bring-up to production or system integration
  • Working fluency across the full silicon lifecycle: architecture, front-end design, verification, FPGA/emulation, physical design, DFT, signoff, package and substrate design, foundry manufacturing, bring-up, ATE, and reliability/qualification
  • Direct experience managing foundry, IP vendor, OSAT, and design-services relationships, including tapeout logistics and mask releases
  • Enough technical depth to communicate credibly with engineers across the design stack, pressure-test schedules, and understand the technical substance of the risks you are driving
More about this role

The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.

Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.

We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.

Join us and shape...

Read the full posting on Neurophos's site ↗

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