Backed by a16z, Kleiner Perkins and Lightspeed.
About the role
At Nexthop AI, we are searching for an experienced Signal Integrity Engineer to own the high-speed channel design of our next-generation switch platforms. If you've spent your career finding out where the textbook answers stop working, and you want to do that at 224G PAM4 and beyond on hardware that ships, we'd love to have you on our team.
What they're looking for
- Own signal integrity end to end for one or more switch platforms: pre-layout feasibility, channel architecture, simulation sign-off at design release, and link-performance debug through EVT and DVT
- Set high-speed channel targets and loss budgets for links at 224G PAM4 per lane and beyond, and defend them against ASIC SerDes capability, module requirements, and cost and manufacturability constraints
- Own stackup and material strategy with PCB fab vendors — laminate selection, Dk/Df modeling, impedance and loss coupon coverage, multi-vendor alignment, and DFM closure
- Run compliance and link analysis (COM, ERL, and the evolving IEEE 802.3dj metrics) for C2M and C2C channels across the module ecosystem we support
- Work directly with ASIC, connector, and package vendors on models, launch geometry, and specifications, hold them to what we need
- Improve how the team works: simulation automation in Python, reusable analysis flows, routing and via design rules, and the SI requirements our hardware and layout partners design against
More about this role
At Nexthop AI, we are searching for an experienced Signal Integrity Engineer to own the high-speed channel design of our next-generation switch platforms. If you've spent your career finding out where the textbook answers stop working, and you want to do that at 224G PAM4 and beyond on hardware that ships, we'd love to have you on our team.
About the Role
As a Senior Signal Integrity Engineer, you'll be the SI owner for a full platform, with links running at 224G PAM4 per lane and beyond — from concept-phase feasibility, through stackup freeze and design release, into EVT/DVT link bring-up and debug. You'll set the channel targets and loss budgets that the design is built to, drive stackup and material decisions with our fab partners, and be the person the team turns to when a channel doesn't close. You'll also shape the methodology and design rules the rest of the SI team works from, and mentor engineers earlier in their careers.
What You'll Do
- Own signal integrity end to end for one or more switch platforms: pre-layout feasibility, channel architecture, simulation sign-off at design release, and link-performance debug through EVT and DVT.
- Set high-speed channel targets and...
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