Niobium offers the industry’s first purpose-built fully homomorphic encryption (FHE) hardware accelerator: a custom PCIe card that can accelerate the performance of FHE software by multiple orders of magnitude. Backed by Purple Arch Ventures.
About the role
Founded as a 2021 spinout from Galois, Inc., a world-class security and computing systems research and development company, our team combines decades of experience in advanced semiconductor design with a record of delivering world class solutions. In this role, you will partner closely with Architecture, RTL Design, Verification, DFT, and Power teams to deliver high-performance, power-efficient silicon across cutting edge technology nodes. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- Own and lead all physical design activities from RTL handoff, floorplanning, and PnR through final GDSII delivery
- Define execution strategy, schedules, design methodology, and quality checkpoints for the entire physical design flow
- Physical partitioning and hierarchy definition
- Power grid architecture and clock distribution topology
- DIE size, aspect ratio, and physical constraints
More about this role
About Niobium
At Niobium Microsystems, we develop high performance microelectronic products to enable the secure collection, processing, and distribution of critical data. We are a trusted partner of government research teams and commercial customers whose solutions require lower power, higher efficiency, and proven security.
Founded as a 2021 spinout from Galois, Inc., a world-class security and computing systems research and development company, our team combines decades of experience in advanced semiconductor design with a record of delivering world class solutions.
About This Role
We are seeking a highly experienced ASIC Physical Design to drive the implementation of complex SoC designs from RTL handoff through tapeout. The ideal candidate has 8+ years of hands-on experience in advanced node physical implementation, proven ownership of multiple successful tapeouts, and the ability to lead both technically and organizationally.
In this role, you will partner closely with Architecture, RTL Design, Verification, DFT, and Power teams to deliver high-performance, power-efficient silicon across cutting edge technology nodes.
Responsibilities
End-to-End Physical Implementation...
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