NUVACORE builds for the stratosphere. Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere, from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. Backed by Sequoia.
About the role
Plan & Strategy: Drive the verification scope, strategy, and test plans for architectural correctness — the CPU's behavior and architectural state versus the specification and a golden reference model. Environment Setup: Build, maintain, and scale robust verification environments — including co-simulation against the golden reference model — that compare architectural state end to end.
What they're looking for
- Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience
- 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design
- Strong knowledge of CPU architecture and micro-architecture — the instruction set, architectural state, exceptions, and privilege model — with a good understanding of at least one modern ISA (x86, ARM, or RISC-V)
- Hands-on functional verification: test plans, testbenches, checkers, and coverage
- Proficiency in C/C++/Rust and/or SystemVerilog, plus a scripting language (Python, Perl a plus)
- Experience writing and debugging tests in assembly for CPU verification
More about this role
Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at multiple levels — from Senior Engineer to Principal level — to help prove that the Nuvacore CPU is architecturally correct. As part of the design verification (DV) team , you will help drive architectural verification — checking the CPU's behavior and architectural state against the architecture specification and a golden reference model — building the stimulus, checkers, and flows that find architectural bugs long before silicon, working shoulder-to-shoulder with architecture and RTL design.
Plan & Strategy: Drive the verification scope, strategy, and test plans for architectural correctness — the CPU's behavior and architectural state versus the specification and a golden reference model.
Environment Setup: Build, maintain, and scale robust verification environments — including co-simulation against the golden reference model — that compare architectural state end to end.
Test & Debug: Generate stimulus in assembly and random instruction sequences (RIS) to exercise the full instruction set and architectural corner cases such as...
Browse similar: AI jobs · AI startup jobs · Startup jobs