NUVACORE builds for the stratosphere. Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere, from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. Backed by Sequoia.
About the role
As a Custom Clock Design and Distribution (CCD) Engineer, you will participate in the following : Architect and drive the end-to-end clock generation and distribution methodology using H-tree, mesh, spine, and multi-source clock-tree synthesis for high-frequency CPU cores, co-optimizing skew, insertion delay, jitter, duty-cycle distortion, and clock power.
What they're looking for
- Hold a BS or MS degree with 12+ years of experience (for Lead roles) or 5+ years of experience (for Individual Contributor roles) in clock design, clock distribution, and/or custom circuit design
- Hands-on transistor-level design experience with clock dividers, deskew and duty-cycle correction, clock-gating and mux cells at advanced CMOS nodes
- Proven experience constructing and analyzing low-skew, low-power clock distribution networks using H-tree, mesh, spine, and multi-source CTS for high-frequency CPUs
- Strong SPICE simulation and analysis skills, with solid grounding in device physics, RC delay, and signal integrity applied to clock-path design and verification
- Well-versed in STA and clock timing signoff including setup, hold, duty cycle closure across Functional and DFT (Design for Test) modes
- Demonstrated track record delivering clock networks and/or clocking IP through tape-out, with silicon-validated PPA — frequency, skew, jitter, and power — in high-volume products
More about this role
Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As a member of the CPU clock design team, you will architect and deliver the clock generation and distribution networks that set the frequency, skew, jitter, and power ceiling for the product.
As a Custom Clock Design and Distribution (CCD) Engineer, you will participate in the following :
Architect and drive the end-to-end clock generation and distribution methodology using H-tree, mesh, spine, and multi-source clock-tree synthesis for high-frequency CPU cores, co-optimizing skew, insertion delay, jitter, duty-cycle distortion, and clock power.
Design and characterize custom clock circuits at transistor level clock buffers and repeaters, dividers, deskew and duty-cycle correction, clock-gating and clock-mux cells meeting PPA targets across PVT corners.
Own end-to-end clock-network closure: SPICE-driven skew, latency, and jitter analysis, EM/IR and signal-integrity signoff on the clock grid, and STA correlation (OCV/AOCV/POCV) across Functional and DFT modes.
Partner with PLL/FLL, timing, power, CAD, physical design, and DFT teams aligning clock source models, jitter budgets, and...
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