NUVACORE builds for the stratosphere. Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere, from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. Backed by Sequoia.
About the role
As a Custom Design Lead, you will participate in and direct work in the following : Lead a small team of engineers responsible for development of custom memories (SRAM and register files) used in development of a high performance CPU Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- Hold a BS, MS, or PhD degree with 12+ years of experience in custom memory circuit design - SRAMs, and/or Register files
- Hands-on transistor-level circuit design experience with combo cells, sequential logic in static/dynamic logic families, as well as memory arrays — bit cells, sense amps, decoders — in advanced CMOS nodes
- Deep knowledge of SPICE simulations, SRAMs / Register File circuit margins, and special memory cells architecture
- Proficient with industry-standard EDA tools for schematic, layout, extraction, and characterization, applied to custom memory design workflows
- Demonstrated track record delivering production-level custom memory IP through tape-out, with silicon-validated PPA in high-volume products
- Deep understanding of end-to-end signoff for custom memories — DRC/LVS/antenna, extraction, Spice margins, STA, EM/IR — and characterization flows spanning timing, power, and noise
More about this role
Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As a member of the CPU-specific custom circuit design team, you will enable the design to achieve the target PPA specifications for the product.
As a Custom Design Lead, you will participate in and direct work in the following :
Lead a small team of engineers responsible for development of custom memories (SRAM and register files) used in development of a high performance CPU
Manage and help participate in schematic development and characterization of custom memories (SRAM, register files) to optimize PPA at advanced process nodes.
Supervise layout implementation, defining macro floor planning, critical routing specifications, and driving physical design verification (PDV) closure.
Manage engineers performing end-to-end memory IP signoff: schematic and layout through DRC/LVS/antenna, parasitic extraction, and characterization (timing, power, and noise in Liberty/CCS format) across PVT corners, meeting target PPA commitments.
Partner with Foundry/PDK, CAD, Physical Design, RTL and DFT teams to benchmark new process technology, validate IP on testchips, and co-optimize custom...
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