NUVACORE builds for the stratosphere. Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere, from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. Backed by Sequoia.
About the role
Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As DFT engineers within the CPU team you will be responsible for test related pre-silicon and post-silicon activities. We will be delivering a DFT architecture which aligns with the projects industry leading power, performance, and area.
What they're looking for
- BS or MS with 7 years experience in DFT or DFT verification
- Scan or MBIST with industry standard EDA tools, or experience with DFT verification flows
- For scan role, able to define scan insertion, scan compression, and clking requirements, and define intest and extest modes
- For MBIST role, be very familiar with memory repair, and repair interaction with functional operation
- Strong understanding of JTAG, IEEE 1500 and IEEE 1687
- Experience with Verilog RTL and gate level netlists, including running and debugging simulations
More about this role
Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As DFT engineers within the CPU team you will be responsible for test related pre-silicon and post-silicon activities. We will be delivering a DFT architecture which aligns with the projects industry leading power, performance, and area.
Defining and implementing area and power efficient DFT architecture while collaborating with design, STA and PD
Develop scan and BIST insertion flows, implement DFT registers in design blocks
Completing DFT architecture specifications
Review and integrate third party IPs into DFT architecture
Define verification plans for DFT features
Review DFT coverage for scan and MBIST
Verification of DFT features in RTL and gates, and power aware simulations
Generate test content for silicon bringup, and support silicon bringup activities including yield analysis
BS or MS with 7 years experience in DFT or DFT verification
Scan or MBIST with industry standard EDA tools, or experience with DFT verification flows
For scan role, able to define scan insertion, scan compression, and clking requirements, and define intest and extest modes
For MBIST role, be very...
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