NUVACORE builds for the stratosphere. Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere, from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. Backed by Sequoia.
About the role
Plan & Strategy: Drive the verification scope, strategy, and test plans for the interconnect fabric — coherent and non-coherent, including crossbars, routing, and bus interfaces. Environment Setup: Build, maintain, and scale robust verification environments — stimulus generators, protocol checkers, transactors, and coverage — that exercise coherent and non-coherent transactions end to end.
What they're looking for
- Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience
- 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design
- Strong knowledge of interconnect/fabric architecture and digital logic — coherent and non-coherent protocols (e.g. AMBA, CHI, TileLink) and on-chip transport
- Hands-on functional verification: test plans, testbenches, protocol checkers, transactors, and coverage
- Proficiency in C/C++/Rust and/or SystemVerilog, plus a scripting language (Python, Perl a plus)
- Experience writing and debugging tests for complex digital designs
More about this role
Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at multiple levels — from Senior Engineer to Principal level — to help prove the correctness of the Nuvacore interconnect fabric. As part of the design verification (DV) team , you will help verify the coherent and non-coherent interconnect — building the test plans, environments, and checkers that find deep bugs in transport, ordering, and coherence long before silicon, working shoulder-to-shoulder with architecture and RTL design.
Plan & Strategy: Drive the verification scope, strategy, and test plans for the interconnect fabric — coherent and non-coherent, including crossbars, routing, and bus interfaces.
Environment Setup: Build, maintain, and scale robust verification environments — stimulus generators, protocol checkers, transactors, and coverage — that exercise coherent and non-coherent transactions end to end.
Test & Debug: Generate directed and random traffic to expose corner cases such as ordering, arbitration, QoS, and deadlock/livelock avoidance.
Performance Verification: Partner with architects to correlate RTL against...
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