NUVACORE builds for the stratosphere. Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere, from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. Backed by Sequoia.
About the role
As a CPU Micro-Architect/RTL Engineer, you will participate in the following: Micro-architecture development and specification - starting from a performance driven design strategy, you will work with our performance modeling team and study early micro-architectures and converge on a design captured in a detailed specification. Critical understanding of the various pipelines and intra-unit communication will be necessary to build a clean, yet, performant design.
What they're looking for
- BS or MS with 15+ (leads) and 7+ (ICs) years experience in high-performance, low-power CPU design
- Experience with coding in Verilog, debugging, simulation, ideal experience in driving modern AI engines to assist in RTL coding
- Solid understanding in logic and physical design and the impacts on timing, power, and area
- Experience with RISC-V or ARM64 or x86 ISA and their impacts on CPU micro-architectural choices
- Strong background in low power microarchitecture and high-performance design techniques, with a proven track record of execution on multiple CPU programs and productions
- Experience in C, C++, and other languages such as Perl or Python
More about this role
Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As engineers within the CPU team and as leads of CPU units (fetch, decode/rename, scalar execute, fp/vector execute, load/store, memory management/TLB, prefetching, debug/trace, system/IO, and multi-level cache subsystem), you will be writing specifications and develop RTL for the CPU which targets and delivers industry leading power, performance, and area.
As a CPU Micro-Architect/RTL Engineer, you will participate in the following:
Micro-architecture development and specification - starting from a performance driven design strategy, you will work with our performance modeling team and study early micro-architectures and converge on a design captured in a detailed specification. Critical understanding of the various pipelines and intra-unit communication will be necessary to build a clean, yet, performant design.
RTL design - develop and refine RTL which targets the power, performance, area and timing goals. A solid understanding of the modern verilog standards is a plus, enabling you to write RTL which is flexible and robust, configurable, and scalable.
Verification - assist the...
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