NUVACORE builds for the stratosphere. Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere, from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. Backed by Sequoia.
About the role
As a CPU Physical Design (PD) Engineer, you will participate in the following : Lead RTL/micro-architecture feasibility studies, providing actionable feedback to design teams.
What they're looking for
- Hold a BS or MS degree with 12+ years of experience (for Lead roles) or 5+ years of experience (for Individual Contributor roles) in CPU physical design
- Strong foundation in CPU micro-architecture (µArch) concepts and design principles
- Experience in CPU RTL feasibility, including RTL synthesis and floorplanning
- Deep expertise in timing analysis and timing ECO
- Proficiency with Synopsys or Cadence EDA tools for PD in CPU design context
- Demonstrated history of successful production tapeouts
More about this role
Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As physical design engineers focused on design feasibility you will focus on providing power, performance, and area feedback to the RTL team to ensure the design achieves all metrics and targets.
As a CPU Physical Design (PD) Engineer, you will participate in the following :
Lead RTL/micro-architecture feasibility studies, providing actionable feedback to design teams.
Drive PPA outcomes for CPU units with a focus on timing closure and power optimization.
Collaborate cross-functionally with CPU unit owners, custom circuit designers, CAD, RTL/micro-architecture, and performance modeling teams.
Own the RTL intake process for the PD team, enforcing quality standards and ensuring design readiness before RTL handoff.
Hold a BS or MS degree with 12+ years of experience (for Lead roles) or 5+ years of experience (for Individual Contributor roles) in CPU physical design.
Strong foundation in CPU micro-architecture (µArch) concepts and design principles.
Experience in CPU RTL feasibility, including RTL synthesis and floorplanning.
Deep expertise in timing analysis and timing...
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