NUVACORE builds for the stratosphere. Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere, from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. Backed by Sequoia.
About the role
As a CPU Static Timing Analysis (STA) Engineer, you will participate in the following : Responsible for performing timing and noise analysis on designs and rolling up analysis results.
What they're looking for
- Hold a BS or MS degree with 12+ years of experience (for Lead roles) or 5+ years of experience (for Individual Contributor roles) in static timing analysis on high-speed designs
- Knowledge in industry-standard EDA tools and scripting languages
- Understanding various timing and noise analysis checks and corresponding constraints
- Strong communication and collaboration skills
- Possess substantial years of experience in CPU unit-level timing and noise analysis
- Understanding of timing noise models and hierarchical analysis strategies
More about this role
Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As physical design engineers as part of the CPU team you will own CPU units for the full silicon development lifecycle..
As a CPU Static Timing Analysis (STA) Engineer, you will participate in the following :
Responsible for performing timing and noise analysis on designs and rolling up analysis results.
Responsible for verifying the quality of the timing/noise runs and checking analysis coverages
Responsible for working with the design teams on understanding the violations and providing fixing suggestions/strategies as well as constraint refinements when needed.
Responsible for performing ECO generation per design needs.
Develop essential methodologies and infrastructure for Timing Analysis & Design closure.
Responsible for working with the CAD team and providing feedbacks on tool/flow issues or enhancement requests to improve productivity
Hold a BS or MS degree with 12+ years of experience (for Lead roles) or 5+ years of experience (for Individual Contributor roles) in static timing analysis on high-speed designs
Knowledge in industry-standard EDA tools and scripting...
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