Startups · AI

Formal Verification Engineer

NUVACORE · Austin · Hybrid

← All jobs
About NUVACORE

NUVACORE builds for the stratosphere. Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere, from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. Backed by Sequoia.

About the role

Plan & Strategy: Drive the verification scope and formal test plan for each verification problem — turning the micro-architecture specification into the properties to prove. Formal Environment: Build the formal environment — assumptions, constraints, assertions, and cover properties — plus reusable, optimized formal models.

What they're looking for

  • Degree in Electrical/Computer Engineering, Computer Science, or Mathematics, or equivalent practical experience
  • 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, with hands-on formal verification
  • Hands-on formal techniques — model checking and/or equivalence checking — through to proof convergence
  • Strong Verilog/SystemVerilog and assertions / temporal logic
  • Strong knowledge of CPU micro-architecture and digital logic
  • Strong scripting (Python, TCL/Perl a plus), analytical, and debug skills
More about this role

Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Formal Verification Engineers at multiple levels — from Senior Engineer to Principal level — to help prove the Nuvacore CPU correct with formal methods. As part of the design verification (DV) team , you will turn micro-architecture specifications into properties, build the environments to prove them, and use model checking and equivalence checking to exhaustively hunt deep, corner-case bugs — establishing correctness long before silicon, working shoulder-to-shoulder with the design team.

Plan & Strategy: Drive the verification scope and formal test plan for each verification problem — turning the micro-architecture specification into the properties to prove.

Formal Environment: Build the formal environment — assumptions, constraints, assertions, and cover properties — plus reusable, optimized formal models.

Proof & Bug Hunting: Apply model checking, equivalence checking, and abstraction to reach full or bounded proofs, and hunt deep bugs in areas such as cache coherence, memory consistency, and speculative execution.

Debug & Design Feedback: Debug counterexamples...

Read the full posting on NUVACORE's site ↗

DESIGN VERIFICATION

Build your edge while you search

Free tools for founders and investors, plus VC Unfiltered, our take on startups, venture and the people who build them.