NUVACORE builds for the stratosphere. Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere, from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. Backed by Sequoia.
About the role
We're looking for a Lead SoC Architect to own the SoC architecture surrounding our CPU core — fabric, memory, I/O, power, and security. You'll set architectural direction, make the system-level trade-offs, and work across design, verification, physical design, and software to see them through.
What they're looking for
- 20+ years in SoC or system architecture, from definition through tape-out and production
- Deep expertise in coherent/non-coherent interconnect and fabric architecture, home node design, and coherency protocols
- Strong grounding in cache hierarchies and memory controller design (DDR5/DDR6, LPDDR5/LPDDR6)
- Working knowledge of PCIe/CXL I/O architecture and System MMU/IO virtualization
- Experience with die-to-die interconnect and chiplet-based partitioning
- Track record integrating in-house and third-party IP, including direct work with vendors and internal IP teams
More about this role
Nuvacore is building a new general-purpose CPU core for AI-era, data-center-scale workloads. Founded by veteran CPU and system architects from world-class companies and backed by Sequoia Capital, we're a clean-sheet build with no legacy architecture to carry forward.
We're looking for a Lead SoC Architect to own the SoC architecture surrounding our CPU core — fabric, memory, I/O, power, and security. You'll set architectural direction, make the system-level trade-offs, and work across design, verification, physical design, and software to see them through.
Own the overall SoC architecture: processor complex integration, fabric topology, system level cache hierarchy, I/O, power management, and memory subsystem.
Architect the coherent fabric — interconnect/NoC topology, home node design and placement, snoop filtering, and cache coherency protocol (e.g., CHI/ACE-class) — balancing bandwidth, latency, and QoS.
Size, partition, and place system-level caches and determine their interaction with the fabric and home nodes.
Architect the I/O subsystem: PCIe and CXL controller integration and topology.
Drive memory subsystem architecture: DDR5/DDR6 and LPDDR5/LPDDR6 controller design,...
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