The latest generation of AI models achieves breakthrough performance by spending vastly more tokens to solve complex problems. Demand is now compounding faster than the infrastructure beneath it can scale. The constraint sits in how tokens are made. Backed by Creandum.
About the role
As a Senior Analog Layout Designer, you will be working to create layouts for RX/TX lane macros and support lane-level integration.
What they're looking for
- 7+ years of Analog Layout Design experience
- Understanding of the Semiconductor Fabrication process and device/layout cross-sections
- Minimum 3 years of experience with the following TSMC FinFET processes: 2nm, 3nm, 4nm, 5nm
- Several tape-outs with FinFET processes, owning major layout macros (ADC, DAC, TIA, CDR, PLL, BGB, LDO)
- Expert-level knowledge of block/macro floor-planning, block integration, routing, clock distribution, and power grid implementation
- Expert-level knowledge of layout considerations for device matching, symmetry, parasitic reduction, and noise isolation
More about this role
AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.
As a Senior Analog Layout Designer, you will be working to create layouts for RX/TX lane macros and support lane-level integration.
7+ years of Analog Layout Design experience
Understanding of the Semiconductor Fabrication process and device/layout cross-sections
Minimum 3 years of experience with the following TSMC FinFET processes: 2nm, 3nm, 4nm, 5nm
Several tape-outs with FinFET processes, owning major layout macros (ADC, DAC, TIA, CDR, PLL, BGB, LDO)
Expert-level knowledge of block/macro floor-planning,...
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