Design a chip in minutes. Backed by Y Combinator.
About the role
We’re looking for engineers who think in terms of intermediate representations and passes — people who can design the data models that physical-design tools run on, not just use them. You should be able to move seamlessly between high-level IR design and low-level performance work, building the infrastructure that lets placement, routing, and timing engines operate at massive scale.
What they're looking for
- Strong background in compilers or IR design (LLVM, MLIR, TVM, CIRCT, or equivalent experience)
- Proficiency in Rust for low-level systems work, Python for tooling and pipelines
- Experience designing data structures for large graphs / sparse relations / geometric data
- Understanding of incremental computation, dependency tracking, and versioning of IR states
- Ability to reason about correctness, determinism, and reproducibility in complex toolchains
- Comfortable digging into massive designs and fixing pathological corner cases
More about this role
Partcl is ending the hardware lottery .
We are developing the next generation of chip design automation tools with a focus on performance, scalability and productivity. We envision a future where hardware engineers benefit from advances in AI and believe the first place to start is with advanced optimization tools.
We’re looking for engineers who think in terms of intermediate representations and passes — people who can design the data models that physical-design tools run on, not just use them. You should be able to move seamlessly between high-level IR design and low-level performance work, building the infrastructure that lets placement, routing, and timing engines operate at massive scale.
At Partcl, we’re not here to play it safe - we’re here to win. We want people who wake up every day wanting to win too. If you are interested in solving massive-scale problems in physical AI, come join us.
- Design the core intermediate representations that physical-design tools use to reason about chips
- Build compiler-like pipelines that lower, normalize, and transform design data across stages (netlist → floorplan → PnR → sign-off)
- Architect the physical-design data model as a...
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