About Positron AI Positron AI specializes in developing custom hardware systems to accelerate AI inference. Backed by NEA.
About the role
Positron AI is building next-generation AI inference accelerators, starting with our first ASIC, Asimov, with additional generations already underway. As Principal DFT Engineer, you'll own DFT and DFx strategy end-to-end: defining the DFT architecture for our accelerators, integrating it into internal RTL and third-party IP, driving implementation with our backend design partner, and ensuring high-quality silicon bring-up through comprehensive pre-silicon validation.
What they're looking for
- Define and maintain the DFT architecture for Asimov and future ASIC generations
- Develop long-term DFT and DFx roadmaps aligned with product quality, manufacturing, yield, diagnostics, and reliability objectives
- Establish DFT design standards, review processes, signoff criteria, and best practices across the engineering organization
- Architect and implement scan insertion, compression, ATPG, memory BIST, logic BIST (where appropriate), boundary scan / IEEE 1149.x, IJTAG / IEEE 1687 infrastructure, and debug/observability features
- Integrate DFT into internally developed RTL
- Evaluate and integrate DFT capabilities from third-party IP providers
More about this role
Role Overview
Positron AI is building next-generation AI inference accelerators, starting with our first ASIC, Asimov, with additional generations already underway. As Principal DFT Engineer, you'll own DFT and DFx strategy end-to-end: defining the DFT architecture for our accelerators, integrating it into internal RTL and third-party IP, driving implementation with our backend design partner, and ensuring high-quality silicon bring-up through comprehensive pre-silicon validation. This is a hands-on, technical ownership role spanning architecture through tapeout and into first silicon, not a coordination role.
Key Responsibilities
Own the Positron DFT strategy
- Define and maintain the DFT architecture for Asimov and future ASIC generations.
- Develop long-term DFT and DFx roadmaps aligned with product quality, manufacturing, yield, diagnostics, and reliability objectives.
- Establish DFT design standards, review processes, signoff criteria, and best practices across the engineering organization.
Hands-on DFT implementation
- Architect and implement scan insertion, compression, ATPG, memory BIST, logic BIST (where appropriate), boundary scan / IEEE 1149.x, IJTAG / IEEE 1687...
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