About Positron AI Positron AI specializes in developing custom hardware systems to accelerate AI inference. Backed by NEA.
About the role
As Emulation Test Engineer, you'll provide technical direction for pre-silicon validation of Positron's next-generation AI inference ASIC. You'll own the end-to-end emulation strategy on the Cadence Palladium platform, architecting complex model builds, managing multi-rack partitioning, and driving the "left-shift" of our software development.
What they're looking for
- Massive-Scale Model Architecture: Lead the partitioning and compilation of our design across a multi-rack Palladium environment, optimizing for performance and debug visibility
- Full-Stack Validation: Design and execute comprehensive emulation test plans to verify high-speed interfaces ( PCIe Gen 6/7, 112G+VSR, Ethernet ) and complex AI memory hierarchies
- Performance & Power Analysis: Utilize Palladium’s Dynamic Power Analysis (DPA) and throughput monitors to identify "true peaks" and performance bottlenecks that simulation cannot capture
- Vendor Management: Act as the primary technical point of contact with Cadence R&D to troubleshoot tool issues and leverage the latest Palladium Z3 capabilities
- Deep Palladium Expertise: Extensive hands-on experience with Cadence Palladium (Z1/Z2/Z3) , including advanced clocking, ICE (In-Circuit Emulation), and Virtual Interface (VIF) flows
- Complex SoC Background: A track record of emulating multi-billion gate designs where partitioning, runtime predictability, and compile efficiency were critical success factors
More about this role
About the role
As Emulation Test Engineer, you'll provide technical direction for pre-silicon validation of Positron's next-generation AI inference ASIC. You'll own the end-to-end emulation strategy on the Cadence Palladium platform, architecting complex model builds, managing multi-rack partitioning, and driving the "left-shift" of our software development. You'll collaborate across RTL, DV, and Software teams to build high-performance virtual environments that prove out architectural functionality and accelerate firmware/OS bring-up months before tape-out. This role is critical to our silicon success: you'll set the emulation methodology, resolve hardware-software bottlenecks at scale, and ensure our design is silicon-ready.
What you'll do
- Massive-Scale Model Architecture: Lead the partitioning and compilation of our design across a multi-rack Palladium environment, optimizing for performance and debug visibility.
- Software Enablement (Left-Shift): Create and maintain the hybrid emulation and co-simulation environments (using SCE-MI or DPI ) that allow our software teams to boot OS images and run AI workloads on pre-silicon hardware.
- Full-Stack Validation: Design and...
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