About Positron AI Positron AI specializes in developing custom hardware systems to accelerate AI inference. Backed by NEA.
About the role
We're looking for an exceptional Principal Mid-End ASIC Engineer to own synthesis, timing convergence, implementation readiness, and logical design quality across our AI accelerator roadmap. This is a deeply technical, hands-on engineering role responsible for transforming high-quality RTL into implementation-ready netlists while driving timing closure strategy, constraint development, physical-aware optimization, and close collaboration between RTL designers and backend implementation partners.
What they're looking for
- 12+ years of ASIC implementation experience, including multiple successful tapeouts
- Expert-level proficiency in synthesis methodology and flow development
- Deep expertise in timing closure across complex, multi-million-gate designs
- Expert-level command of Cadence Genus and/or Synopsys Design Compiler
- Strong SDC expertise, including constraint development and MMMC environments
- A solid grasp of RTL design principles and implementation-friendly coding practices
More about this role
We're looking for an exceptional Principal Mid-End ASIC Engineer to own synthesis, timing convergence, implementation readiness, and logical design quality across our AI accelerator roadmap. This is a deeply technical, hands-on engineering role responsible for transforming high-quality RTL into implementation-ready netlists while driving timing closure strategy, constraint development, physical-aware optimization, and close collaboration between RTL designers and backend implementation partners. You will serve as the technical bridge between architecture, RTL, verification, and physical implementation.
Synthesis Methodology & Ownership
- Define and own synthesis methodology across current and future ASIC generations, including scalable flows for RTL synthesis, constraint development, timing budgeting, QoR optimization, incremental synthesis, and hierarchical implementation.
- Establish signoff criteria and methodology for synthesis deliverables.
Hands-On Synthesis & Constraint Development
- Own hands-on synthesis using industry-leading EDA tools, including Cadence Genus and Synopsys Design Compiler (or equivalent).
- Develop and maintain SDC constraints, clock definitions, false...
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