Practical quantum computing. Delivered over the cloud. Backed by a16z and Alchemist.
About the role
Lead experimental programs to characterize, calibrate, and optimize two-qubit gates on tunable-coupler devices, from single-pair physics investigations to full-processor deployment. Identify gate-error bottlenecks (e.g., coherent control error, decoherence, leakage, crosstalk, TLS interactions) for single-pair as well as large-scale systems and isolate their physical origin through targeted experiments, benchmarking, and simulation.
What they're looking for
- PhD in Physics, Applied Physics, Electrical Engineering, or a related field
- Significant hands-on experience calibrating and characterizing two-qubit gates on superconducting quantum devices, direct experience with tunable couplers is a strong plus
- Deep understanding of gate design, pulse engineering, and decoherence mechanisms, with a track record of connecting error diagnostics to concrete fidelity improvements
- Demonstrated ability to independently execute complex experimental efforts from concept to validated result
- Strong Python skills in a scientific context, and comfort building tools that others rely on
- Dogged experimental determination, with the judgment to balance depth of investigation against speed of iteration
More about this role
We are looking for an experienced Quantum Engineer to drive the two-qubit gate performance of our tunable-coupler superconducting quantum processors.
Two-qubit gate fidelity is one of the most consequential challenges in quantum computing, and it sits at the center of our roadmap toward error correction. In this role, you will design, execute, and interpret the experiments that propel our near- and long-term gate performance at scale. You will identify the dominant sources of two-qubit gate error on our processors, isolate their physical origin, and eliminate them — through pulse engineering, calibration methodology, error suppression strategies, or feedback to design and fabrication. Your conclusions will directly inform device design, control strategy, and platform-level decisions.
This is a role with substantial autonomy and ownership. You will directly influence the technical direction for gate performance work through the rigorous design and execution of your test plans, measurement and improvement of relevant metrics and error budgeting, and shaping of research priorities. You will do this in a deeply collaborative environment spanning device design, fabrication, control...
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