Develop frontier language models and agents. Training, reinforcement learning, and inference in one system, on River Cloud or your own GPU cluster. Backed by General Catalyst.
About the role
We are seeking an emulation-focused design verification engineer to drive IP and SoC verification on emulation platforms. Working with simulation-based DV teams, you will translate architectural and microarchitectural definitions into workloads suited to emulation, then adapt and run those tests. You will partner with DV block owners on debug and emulation-specific closure, providing emulation signoff as an input to overall verification signoff.
What they're looking for
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, and 5+ years of industry experience
- Hands-on experience with platforms such as Cadence Palladium/Protium, Synopsys ZeBu/HAPS, or comparable systems, including bring-up, model integration, compilation, execution, and debug
- Experience building or adapting models and test environments for simulation acceleration, emulator-hosted verification, or both
- Strong understanding of verification planning, regression strategy, and verification closure, with the ability to translate DV goals into emulation workload and run criteria
- Experience verifying complex IP or SoCs, with an understanding of how verification needs change from block-level to system-level testing
- Proficiency in SystemVerilog, C/C++, and scripting languages such as Python, Tcl, or Bash
More about this role
At River AI, our mission is to create personal AI owned and shaped by each individual. To achieve this, we are rewriting the entire stack from scratch: personal hardware for local inference, bespoke training infrastructure, next-generation UIs, and frontier deep learning research.
We are scientists, engineers, and builders from the industry's top tech companies and AI labs. We bring a proven track record of scaling consumer systems for hundreds of millions of users and architecting the pre-training infrastructure behind today's frontier models.
We are seeking an emulation-focused design verification engineer to drive IP and SoC verification on emulation platforms. Working with simulation-based DV teams, you will translate architectural and microarchitectural definitions into workloads suited to emulation, then adapt and run those tests. You will partner with DV block owners on debug and emulation-specific closure, providing emulation signoff as an input to overall verification signoff. You will also develop the models and infrastructure needed to support this work.
- Verification Strategy & Planning : Translate IP and SoC verification plans into execution strategies, mapping tests...
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