Develop frontier language models and agents. Training, reinforcement learning, and inference in one system, on River Cloud or your own GPU cluster. Backed by General Catalyst.
About the role
We are seeking exception design verification engineers to ensure our high-performance custom silicon is functionally correct. Starting from architectural and micro-architectural definitions, you will define test bench boundaries and implement test environments across a variety of verification methodologies (simulation, formal, emulation, etc). You will collaborate with RTL design, performance modeling and verification, and compiler teams.
What they're looking for
- Bachelor’s degree in Electrical Engineering or Computer Engineering or Computer Science, and 5+ years industry experience
- Deep, hands-on experience building UVM-based environments (Agents, Scoreboards, Drivers, Monitors, and Predictors)
- Expert command of SystemVerilog for verification, including OOP principles, randomization, and functional coverage
- Strong understanding of computer architecture, including pipelines, cache coherency protocols, memory consistency models, and high-speed interconnects (e.g., AXI, CHI)
- Proven track record of verifying high-performance silicon (CPU, GPU, AI accelerator, or complex SoC)
- A highly collaborative mindset and a bias for action to push boundaries and co-design effectively with other engineers
More about this role
At River AI, our mission is to create personal AI owned and shaped by each individual. To achieve this, we are rewriting the entire stack from scratch: personal hardware for local inference, bespoke training infrastructure, next-generation UIs, and frontier deep learning research.
We are scientists, engineers, and builders from the industry's top tech companies and AI labs. We bring a proven track record of scaling consumer systems for hundreds of millions of users and architecting the pre-training infrastructure behind today's frontier models.
We are seeking exception design verification engineers to ensure our high-performance custom silicon is functionally correct. Starting from architectural and micro-architectural definitions, you will define test bench boundaries and implement test environments across a variety of verification methodologies (simulation, formal, emulation, etc). You will collaborate with RTL design, performance modeling and verification, and compiler teams.
- Verification Strategy & Planning: Define comprehensive verification plans by extracting features from architectural and micro-architectural specifications for complex blocks.
- UVM Environment...
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