One core technology. Comms and sensing. Backed by Space Capital.
About the role
We're looking for a Senior DFT Engineer who can own Design-for-Test from architecture through ATPG, silicon bring-up, and production test for our phased-array ASIC and FPGA solutions. As one of our early senior digital hires, you will define the test architecture that makes complex beamforming and adaptive-processing silicon manufacturable, diagnosable, and field-reliable—bridging RTL to ATE and first silicon.
What they're looking for
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
- 7–10 years of relevant DFT experience on ASICs or large FPGAs
- Hands-on experience with industry DFT tools (e.g., Siemens Tessent, Synopsys TestMAX) including scan insertion, compression, MBIST, and ATPG
- Proven ability to verify DFT in simulation and take patterns to silicon or FPGA
- Solid understanding of RTL (SystemVerilog/Verilog), STA/test-mode constraints, and CDC/lint implications of DFT logic
- Demonstrated ability to work across RTL, synthesis, PD, and test engineering
More about this role
Roguebeam is a startup developing advanced phased array systems for communications and radar applications. We design and manufacture complete systems in-house—RF, antenna, PCB, ASIC/digital, and DSP—giving our engineers end-to-end ownership of the technology and a direct line of sight from algorithm to deployed system.
We’re early, we’re growing fast, and the people who join us now will shape both the technology and the company.
We're looking for a Senior DFT Engineer who can own Design-for-Test from architecture through ATPG, silicon bring-up, and production test for our phased-array ASIC and FPGA solutions. As one of our early senior digital hires, you will define the test architecture that makes complex beamforming and adaptive-processing silicon manufacturable, diagnosable, and field-reliable—bridging RTL to ATE and first silicon.
You'll work end-to-end: DFT architecture, scan/BIST insertion, pattern generation, gate-level verification, timing/test-mode constraints with synthesis and PD, and lab/ATE validation. The decisions you make will directly shape yield, test cost, and product quality.
Define and implement hierarchical and full-chip DFT architecture for digital...
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