One core technology. Comms and sensing. Backed by Space Capital.
About the role
We're looking for a Senior Synthesis / Timing Engineer who can own constraints, logical synthesis, and static timing from RTL through sign-off for our phased-array ASIC and FPGA solutions. As one of our early senior digital hires, you will make the beamforming and adaptive data paths meet throughput, latency, and power—bridging algorithm RTL to a timing-clean netlist that PD can close.
What they're looking for
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
- 7–10 years of relevant experience in synthesis and STA for ASICs or large FPGAs
- Strong hands-on experience with industry tools (e.g., Design Compiler / Fusion Compiler / Genus, PrimeTime or Tempus)
- Proven production-quality SDC, multi-mode multi-corner timing closure, and ECO methodology
- Solid RTL literacy (SystemVerilog/Verilog) and ability to work with DSP-heavy, high-utilization designs
- Demonstrated ability to translate performance requirements into implementable constraints and closed timing
More about this role
Roguebeam is a startup developing advanced phased array systems for communications and radar applications. We design and manufacture complete systems in-house—RF, antenna, PCB, ASIC/digital, and DSP—giving our engineers end-to-end ownership of the technology and a direct line of sight from algorithm to deployed system.
We’re early, we’re growing fast, and the people who join us now will shape both the technology and the company.
We're looking for a Senior Synthesis / Timing Engineer who can own constraints, logical synthesis, and static timing from RTL through sign-off for our phased-array ASIC and FPGA solutions. As one of our early senior digital hires, you will make the beamforming and adaptive data paths meet throughput, latency, and power—bridging algorithm RTL to a timing-clean netlist that PD can close.
You'll work end-to-end: SDC and multi-mode constraints, synthesis, STA, ECO loops, lint/CDC/formal handoff, and support for place-and-route and lab validation. The decisions you make will directly shape system capability and product differentiation.
Own synthesis flows and SDC for DSP data paths, beamforming engines, control logic, and high-speed interfaces (multi-clock,...
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