SiTime is a leader in MEMS timing solutions, having shipped billions of units. Learn about our silicon MEMS oscillators, TCXOs, OCXOs, MEMS resonators, clock generators, jitter cleaners, clock timing, timing clock, sitm stock, and much more. Backed by NEA.
About the role
The Senior Layout Design Engineer will lead top-chip, block-level and perform custom Analog Layout Design for CMOS and BiCMOS circuits. This role includes reviewing and coordinating work performed by offshore layout designers, training junior layout engineers and offshore contractors, contributing to the development of standard layout methodologies across sites, and helping establish processes and procedures that ensure high-quality layout design Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- BA/BS degree in Layout Design or a related field, or equivalent experience
- 15+ years of experience in layout design for analog and full-custom digital blocks
- Experience with TSMC 180nm, 65nm, 22nm process technologies
- Proficiency with layout editing tools in the Cadence Virtuoso design environment
- Solid working knowledge of DRC, LVS, and ERC debugging using Cadence PVS or Mentor Calibre
- Understanding of layout concepts, including parasitics, matching, crosstalk, layout-dependent effects, latch-up, IR drop, electromigration (EM), and deep N-well and NTN isolation
More about this role
SiTime is the Precision Timing company.
Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.
Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com .
The Senior Layout Design Engineer will lead top-chip, block-level and perform custom Analog Layout Design for CMOS and BiCMOS circuits. This role includes reviewing and coordinating work performed by offshore layout designers, training junior layout engineers and offshore contractors, contributing to the development of standard layout...
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