Sygaldry builds quantum-accelerated AI servers to exponentially speed up AI training and inference, cutting compute costs and improving energy efficiency. Backed by Y Combinator.
About the role
Develop theoretical and numerical models of qubit devices, gate operations, and physical-layer processes to guide next-generation processor design Design and evaluate system architectures under hardware-specific constraints and realistic noise models
What they're looking for
- A PhD in physics, applied physics, computer science, electrical engineering, or an equivalent degree in a similar field
- 5–10 years of experience in the theory and modeling of quantum computing hardware
- Publications in quantum device physics, quantum architecture, or related fields
- Strong programming skills in a scientific computing environment
- Proven track record of successful cross-team collaborative projects
- Excellent written and verbal communication skills
More about this role
Sygaldry Technologies is building quantum-accelerated AI servers to exponentially speed up training and inference for AI. By integrating quantum and AI, we're accelerating the path to super intelligence, and engineering the conditions for it to scale efficiently and operate affordably. Sygaldry AI servers combine multiple qubit types within a single, fault-tolerant architecture to deliver the combination of cost, scale, and speed necessary for advanced AI applications. We pioneer new domains in physics, engineering, and AI, tackling the hardest challenges with a grounded, optimistic, and rigorous culture. We're looking for individuals ready to define the intersection of quantum and AI and drive its profound global impact.
Develop theoretical and numerical models of qubit devices, gate operations, and physical-layer processes to guide next-generation processor design
Design and evaluate system architectures under hardware-specific constraints and realistic noise models
Translate device-level physics into architecture-level requirements, and architecture-level goals into concrete device specifications
Determine error budgets and gate fidelity requirements from architecture-level...
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